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Programming Interface for Bus Master IDE Controller Revision 1.0
+ l9 x' O" O; H1 ^" `2 D7 _& O! m1994/05/16# L2 g/ a( K1 f" W' d; [3 ~
5 `) S. L* x, `5 f' f
This document defines a register level programming interface for a bus master ATA compatible (IDE) disk
$ J) t9 l6 p( o( p4 xcontroller that directly moves data between IDE devices and main memory. By performing the IDE data$ y0 V/ C* F+ v# x( z3 X J
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
: r& B" t, Q- s" r. m5 I, u% ?$ Y$ Cand improves system performance in multitasking environments.# A, ]$ p6 \0 }! V% q7 V; T2 _
- R& N1 C. P/ o0 fUntil this specification is ratified, it is solely
* [1 M3 I6 t; y t9 vowned and maintained by:: t3 T* w$ u! G$ M! M2 ^* |
Brad Hosler, Intel Corporation
: e0 t7 n- n; v& Y7 n/ Lbwh@salem.intel.com (please comment using email)
7 `- ~7 \0 [1 i8 U503-696-8431 |
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发表于 2010-7-14 14:53:56
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