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Programming Interface for Bus Master IDE Controller Revision 1.0
# h0 u5 H7 j4 c9 T) a T1994/05/16
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk0 E9 {3 R. B5 [$ @" w& x- O2 N
controller that directly moves data between IDE devices and main memory. By performing the IDE data7 q' _# \0 i" F% ]/ j
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
& ?8 a/ X p3 U9 Pand improves system performance in multitasking environments.
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6 l1 a- e3 v, \. N9 J8 }' vUntil this specification is ratified, it is solely7 a2 Y4 c; {1 l: X/ b# T
owned and maintained by:2 v2 w. W' j/ E
Brad Hosler, Intel Corporation
( a! ^6 w3 V) mbwh@salem.intel.com (please comment using email)3 }# }6 r: D0 d W) _+ n
503-696-8431 |
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