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Programming Interface for Bus Master IDE Controller Revision 1.0
* I, E* L: f5 Y6 i1994/05/163 ]3 B' \: f4 i5 r
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk
0 K& |% Z) ?* \5 O+ P8 A7 \controller that directly moves data between IDE devices and main memory. By performing the IDE data
. `0 f/ ~6 s0 U, `! }) jtransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
9 x- E. F9 j' I' D; \and improves system performance in multitasking environments.5 a) U7 I `( M6 Y- F2 o9 g
2 Q8 b, L# v: ]5 U
Until this specification is ratified, it is solely
2 F' k z2 d% C/ G( Z4 q! y4 ]owned and maintained by:
% N5 w' C3 V# m2 K" B2 o( }3 @9 xBrad Hosler, Intel Corporation, \/ J/ ^$ M" u. @' \
bwh@salem.intel.com (please comment using email)
" `2 Q! V4 t* \8 A$ Q; A: \503-696-8431 |
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发表于 2010-7-14 14:53:56
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