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Programming Interface for Bus Master IDE Controller Revision 1.0
6 N2 ~9 u! G0 e" ^" B1994/05/16- N/ n. w/ B, c5 B D% f
7 U+ V4 |, U8 `$ H3 nThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk- f: U: j+ H$ K* Z( q, ? f' o
controller that directly moves data between IDE devices and main memory. By performing the IDE data! N7 ~) x3 J3 j, i6 Z) Q/ j! ~2 z: P
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
9 e' j9 S. J1 I1 F' s& B0 O1 tand improves system performance in multitasking environments.
3 g/ d& S' O* h( `/ S% |& v% h) |& t
Until this specification is ratified, it is solely
+ x0 O% C* q% i6 ]* r: u4 Gowned and maintained by:
7 e( [! p; J H5 mBrad Hosler, Intel Corporation
1 X/ L6 N2 B5 z4 r9 \( B0 k% t# Tbwh@salem.intel.com (please comment using email): D" i' c) _; L, D0 p
503-696-8431 |
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发表于 2010-7-14 14:53:56
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