Programming Interface for Bus Master IDE Controller Revision 1.0

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Programming Interface for Bus Master IDE Controller Revision 1.0
1994/05/16
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk
5 a! C0 Z: |* c7 n" |, N: Pcontroller that directly moves data between IDE devices and main memory. By performing the IDE data
) X& C6 ~5 J! A5 M# etransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
9 J5 Y: ^+ [* K% P# Dand improves system performance in multitasking environments.

( I. ]1 Y" M& V: {& b6 bUntil this specification is ratified, it is solely
owned and maintained by:
+ g4 g7 `' X7 O) wBrad Hosler, Intel Corporation
: ~( e4 M3 H$ B/ o4 dbwh@salem.intel.com (please comment using email)
9 z0 Y7 b( G$ Q" J% \4 N6 P# _503-696-8431