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Programming Interface for Bus Master IDE Controller Revision 1.0; y2 A S4 s! ]7 y& H ~2 q
1994/05/16' b. [! V1 p* }3 G6 y
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk# L, F2 V2 c! ^
controller that directly moves data between IDE devices and main memory. By performing the IDE data! [/ t) g* v# U, E$ X
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)' _; X3 c6 S3 C- h* j7 U
and improves system performance in multitasking environments.& j' Y/ }) P! ?1 S
- J9 a* \ \3 R. z% {: `4 `/ w! QUntil this specification is ratified, it is solely
& u, K( i% ~0 K- q/ cowned and maintained by:8 z& R# A! U5 ?7 `1 L+ \, m3 c9 D
Brad Hosler, Intel Corporation; z/ J/ P3 D; E! ?, J' F! o) f
bwh@salem.intel.com (please comment using email)% l2 T; ^, I, q
503-696-8431 |
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发表于 2010-7-14 14:53:56
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