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Programming Interface for Bus Master IDE Controller Revision 1.0, w4 ~& l2 h3 O1 l& ?) Q
1994/05/16
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk
9 v! o8 C7 C) b' }! A" _9 G3 Kcontroller that directly moves data between IDE devices and main memory. By performing the IDE data
3 x7 w$ t B8 ~& O' O( ]- s; stransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)& e9 q3 H" x0 l5 P, }* ^
and improves system performance in multitasking environments.
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6 W/ _& T6 l0 U7 y! r! ^7 g) V" A: ]Until this specification is ratified, it is solely
7 e: D5 k" U& C" j9 @9 _3 Howned and maintained by:' g. H0 e Y9 H/ n( N
Brad Hosler, Intel Corporation
9 m0 N# ]0 R" h1 d1 |) a& Fbwh@salem.intel.com (please comment using email)
$ f9 f: @! L8 w$ O6 O503-696-8431 |
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