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Programming Interface for Bus Master IDE Controller Revision 1.0. ?2 O4 X! e9 G0 ?( A
1994/05/16
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1 F4 W. s, n- z K9 Q3 FThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk! }+ d6 [4 z7 l4 q9 u( W
controller that directly moves data between IDE devices and main memory. By performing the IDE data6 p0 b6 A5 }! V9 T4 j
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
0 Q; H; a& E! m6 L8 w1 Z5 cand improves system performance in multitasking environments.
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Until this specification is ratified, it is solely
' x' d! q4 m. B( `% @! howned and maintained by:7 e: b0 Z! w! N( u! Z* t
Brad Hosler, Intel Corporation2 R# J% s, }9 u0 f# Y L
bwh@salem.intel.com (please comment using email)
: Z+ E" K3 Z& `503-696-8431 |
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