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Feature Summary! b6 T, Z X' o9 d2 c
) E! c/ D Q3 W; M4 B' N! A
Low Pin Count Host Interface (LPC)* N+ f# t' Y7 R2 }
SIRQ supporting IRQ1, IRQ12, SCI
# u5 _3 p7 p7 i4 a I/O Address Decoding:
9 K+ J5 i/ X9 R# L KBC IO Port 60h/64h
4 H8 h! Q9 ~9 a1 R2 _6 [2 F Programmable EC IO Port 62h/66h and 68h/6Ch( P* M9 T' g4 {" @ |
Programmable 4-byte Index I/O ports to access internal registers- j$ S3 ]* D4 F
One Programmable I/O write byte-address decoding5 M. h/ T# Z+ m& M5 W% [+ [( r
$ Y# ~$ L9 ^0 d* ?- Y) n
X-Bus Interface (XBI)* }6 h- M5 T" T' s& _ C# o
SPI Flash support, the operation frequency runs at least 50MHz.) [, I+ T- L5 W
Addressable Memory range up to 24MB." v7 j" I r2 M. G/ L
8051 64KB code memory can be mapped into 4 independent 16KB pages.
4 A* X. Z1 v% [/ n, Z" H1 Z! d7 d, ]& e6 ]8 l" I7 h j0 e
8051 Microprocessor
+ j. }' ?- R" N$ T Industry 8051 Instruction set complaint with 3~5 cycles per instruction., \8 a- }; X* S r+ f
Programmable 8/16/32 MHz clock
0 u* _+ n _: b) W; I# v+ e5 V, O Fast instruction fetching from XBI Interface
; [; S* b' T. n3 Q3 ^ 128 bytes and 2KB tightly-coupled SRAM- C6 y; s" x# @) ^1 C
24 extended interrupt sources.3 Z5 ?3 d. E( D* G1 G
Two 16-bit tightly-coupled timer
/ ] w+ ?' ? ?
7 _3 j' |+ r/ K" k6 p0 m/ `8042 Keyboard Controller7 V* m4 K% A: k8 }: I" ? Q
8 Standard keyboard commands processed by hardware( ~! x% p; z' C) W1 D2 O, w. U
Each hardware command can be optionally processed by firmware% l( J4 }0 B/ M# a
$ s; T% p! b* MEmbedded Controller (EC)
; T" h, r5 A8 z& H" {! G) L Five EC Standard Commands can be processed by hardware0 |, Z; l8 l( ^7 x1 m+ U
ACPI Specification 2.0 compliant$ B* c Z$ V$ J" \8 P) \
Support customer command by firmware! h9 O# ~2 R4 I T
Programmable EC I/O port addressing (default 62h/66h)! ~+ o, d) ^& D E
2 p. D2 v1 a. w8 A$ Q8 G
Analog To Digital Converter (ADC)
! N5 h, z& q# s* z L( f7 ~4 h 6 built-in ADCs with 8-bit resolution.
4 t/ n0 z1 @7 ~ The ADC pins can be alternatively configured as General Purpose Inputs (GPI).! O7 D( U3 B5 T+ v7 V0 `1 I
7 V- G4 N6 p3 a7 t4 c8 MPulse Width Modulator (PWM)6 R" d/ p2 X5 T8 B& _ A
5 built-in PWMs
( k3 N; S/ S; A5 W- |+ H$ \; \) n Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.2 K+ @! {$ R! i- u L7 A, X% o: b: q
Configurable cycle time (up to 1 sec) and duty cycle.
: T8 m. R% ~* j. X- S9 L2 j6 Y! `: t% U8 f6 s: K
Watchdog Timer (WDT)
) R7 P6 R1 l' A9 W( l 32.768KHz input clock with 20-bit time scale.
0 o4 w* v" `0 c. _/ _3 t6 K, [0 W 8-bit watchdog timer interrupt and reset setting9 O! ^6 y1 i; Y M3 ~
( B; A# \9 n% h0 Y$ V( b( N1 xGeneral Purpose Timer (GPT)
& k: h$ U& M5 C( b J+ t' h Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
9 d1 T# _7 p8 F, P0 w2 t2 n T$ E5 r: ?5 I
General Purpose Wake-Up (GPWU)
7 C& g+ q! V& Y' C! k3 P" ` All General Purpose Input pins can be configured to generate interrupts or wake-up event.
* a3 a' ^/ C/ ]+ ~5 R6 r+ i% ]. N4 o4 q. ]6 o1 _9 ?( t* k
General Purpose Input/Output (GPIO)# Q$ m2 l' F: f. A5 l
All I/O pins are bi-direction and configurable2 Z( S1 j# p- j( i
All outputs can be optionally tri-stated
e. r) a; K; Z6 \7 e( n. z- R All inputs equipped with pull-up, high/low active, edge/level trigger selection2 v* t( i. l/ P5 g) j
All GPIO pins are bi-direction, input and output./ B# j3 h3 p5 R* W3 V! Q
Max. 43 GPIOs
5 f7 A% W9 u. T1 V5 K9 f
' x7 B! n9 G6 r$ ]2 x+ {- s* UPower Management
9 Z. g# a: e# a2 G! s8 r5 `2 v Sleep State: 8051 Program Counter (PC) stopped
/ n' _$ G% Y% g- n' D6 _/ L, ~ Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
- B6 K% N$ n7 v6 p, T/ `1 F/ F- F+ I
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