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Feature Summary
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( k; E5 u; j( \' rLow Pin Count Host Interface (LPC)$ N; e, @% y6 s+ Z5 k6 ?) H- h
SIRQ supporting IRQ1, IRQ12, SCI
" M4 W$ J( A: |4 M* ` I/O Address Decoding:
+ D3 ^* y, a" [+ z- P KBC IO Port 60h/64h
8 y5 ~. |, G: E! L0 `! I( C Programmable EC IO Port 62h/66h and 68h/6Ch6 {4 y0 M3 _! s
Programmable 4-byte Index I/O ports to access internal registers
; _: x6 j0 ?* f One Programmable I/O write byte-address decoding
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X-Bus Interface (XBI)
+ V5 D- k; n8 d$ K t% s4 l( c SPI Flash support, the operation frequency runs at least 50MHz.0 j# @! t( _7 @5 z& f9 Y: h% y
Addressable Memory range up to 24MB.( l- b5 u; d: _& t8 ?
8051 64KB code memory can be mapped into 4 independent 16KB pages.
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8051 Microprocessor- T- M6 g/ R1 b6 M! Q; d$ p) J o
Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
& {" t; d% j" I7 E' T; r6 @1 w Programmable 8/16/32 MHz clock) }5 C6 h% d. s( P; j( J
Fast instruction fetching from XBI Interface8 Z9 g2 Q! b* f# J5 h6 F B
128 bytes and 2KB tightly-coupled SRAM ^$ J9 F2 Z J
24 extended interrupt sources.( \4 ?& M- N' G$ W1 W$ _; n0 l t
Two 16-bit tightly-coupled timer
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8042 Keyboard Controller# {& m! R5 t \) `
8 Standard keyboard commands processed by hardware. I0 T5 o' ?3 O. G" w# S8 e) _" h
Each hardware command can be optionally processed by firmware2 ^+ g2 l/ V1 A/ a' Z
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Embedded Controller (EC)5 }9 a( ~# a; i6 p" B* x% w
Five EC Standard Commands can be processed by hardware6 K7 b4 n0 }% ?7 M
ACPI Specification 2.0 compliant4 ?9 k* a% } U* Z+ _
Support customer command by firmware) ^+ q- e0 L* i2 k' E. y
Programmable EC I/O port addressing (default 62h/66h)/ O8 b `$ d3 w: @8 X: ^
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Analog To Digital Converter (ADC)
- h2 |& P, v7 f& ]6 @1 D 6 built-in ADCs with 8-bit resolution.( h% O% a0 O" e, b
The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
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Z# f( M: e5 E# @1 Q7 c( XPulse Width Modulator (PWM)
( C8 Y% H* ~6 h1 C7 F: Z 5 built-in PWMs( f6 J8 z% X# K$ _ N
Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.! J. H. U7 _: z1 n" U* i- x% O0 y
Configurable cycle time (up to 1 sec) and duty cycle.
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' `3 h' o4 @9 oWatchdog Timer (WDT)* z2 l1 t& l7 c ?) _' y8 ^ b
32.768KHz input clock with 20-bit time scale.9 Q @) @$ C9 w9 B1 W4 b, w
8-bit watchdog timer interrupt and reset setting+ K9 }: ?3 W' }$ g+ I
* q3 F: ]* ~+ f2 MGeneral Purpose Timer (GPT)
& @( ~7 y1 [5 C+ J3 K- y+ H/ t8 ?3 L Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution4 C0 ?0 l& v5 V2 c
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General Purpose Wake-Up (GPWU)+ P4 h8 @' P G7 r6 V
All General Purpose Input pins can be configured to generate interrupts or wake-up event.
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General Purpose Input/Output (GPIO)4 y$ a+ U8 { z# W7 m
All I/O pins are bi-direction and configurable' c! ?: o) D1 n; d1 L- n! o
All outputs can be optionally tri-stated
3 h) ?$ w: `4 p' R All inputs equipped with pull-up, high/low active, edge/level trigger selection
9 H9 \3 Q v* Q1 F! k/ c5 \+ t All GPIO pins are bi-direction, input and output.9 C; T% k% ^6 w; ?
Max. 43 GPIOs
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) Z4 T- S: ^* B" g5 L' p; dPower Management
8 [! ~) V Y, Y# j. ` Sleep State: 8051 Program Counter (PC) stopped" v: C# F! a% M9 l( n
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
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& ?, e2 {" q/ ~* QTotal Pages: 40 |
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