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Feature Summary C. R- X0 S0 f E1 Y& c
7 B& q4 q; a4 Z! B' h
Low Pin Count Host Interface (LPC)+ w# D. x: R0 x7 e
SIRQ supporting IRQ1, IRQ12, SCI o4 h6 J. d( K7 ?0 g) J6 K* q7 P" f4 e
I/O Address Decoding:& {3 f4 m7 v# y0 {
KBC IO Port 60h/64h
; q9 p- q! L7 v3 L: ` Programmable EC IO Port 62h/66h and 68h/6Ch: u, X4 v: z: j) H
Programmable 4-byte Index I/O ports to access internal registers
& N8 i" p3 y& r/ g One Programmable I/O write byte-address decoding; x* i3 e+ E, t: p
8 T- L/ B% e8 c- D& u
X-Bus Interface (XBI) }+ d& S6 \( O& u' a) ]1 y2 `
SPI Flash support, the operation frequency runs at least 50MHz.
! g7 y4 M) o5 c+ r6 l- P Addressable Memory range up to 24MB.( s+ g9 g4 F+ y" v; H8 C
8051 64KB code memory can be mapped into 4 independent 16KB pages.8 S% ~4 ^9 A7 {9 d$ C
* \* L" H) g! @2 \. g i
8051 Microprocessor
0 v+ T' e9 [2 y* M: \) t7 }: | Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
. l5 } Z4 w3 y! g" G3 k* o! @ Programmable 8/16/32 MHz clock
8 c; s% }0 ^* U- b9 b! F2 E Fast instruction fetching from XBI Interface1 g' T' K7 Y, K$ o' D
128 bytes and 2KB tightly-coupled SRAM
- Q$ h. h, b( |# O 24 extended interrupt sources.
+ E) [& n( J( `' `; ? Two 16-bit tightly-coupled timer
' V* {5 u; T$ o- e
7 ]" [ `* P# f9 W1 B* Y8042 Keyboard Controller! x- v' q: O' o* ^. O
8 Standard keyboard commands processed by hardware
6 n. C4 w l; r1 V8 q) V7 P/ w8 k Each hardware command can be optionally processed by firmware7 T2 O, _6 G r- w
7 G: Y( \5 }6 h# u$ s4 I
Embedded Controller (EC)
% \* b* U1 K, \: Z" b- W, u+ [) W# q0 p Five EC Standard Commands can be processed by hardware- C5 c( x% A i6 Z0 Q1 L
ACPI Specification 2.0 compliant1 r# K# X' q! U) u/ a0 } B& {
Support customer command by firmware1 R1 |0 c3 \! t( B3 k, \
Programmable EC I/O port addressing (default 62h/66h)
: V# U- n1 a/ U
. t F. N) `% M) Y* g, ^7 vAnalog To Digital Converter (ADC)
2 d. N! [( n; l4 t3 e 6 built-in ADCs with 8-bit resolution.. h, ?! ]6 W) J% q) N4 [
The ADC pins can be alternatively configured as General Purpose Inputs (GPI).( i; h% S0 @+ ~: g/ S0 [
9 i' v8 ~6 M x5 _, G$ m9 ~
Pulse Width Modulator (PWM)
3 g$ V: M8 z5 f- L 5 built-in PWMs
% I+ V& _ X! _$ V) H, p Selectable clock sources: 1MHz/64KHz/4KHz/256Hz./ j$ ]8 x# ~' w3 T( d w- p1 A: K
Configurable cycle time (up to 1 sec) and duty cycle.7 V. ^ B8 l0 m/ q/ U& q
$ G( g- j9 I; r2 B% X* h
Watchdog Timer (WDT)3 }# J+ y5 m& M7 _4 F! q
32.768KHz input clock with 20-bit time scale.$ w5 b6 r0 a1 p* k c/ K
8-bit watchdog timer interrupt and reset setting1 o. t+ s! C- A" v
! ~. u+ |8 h& H! t# N, N1 h9 fGeneral Purpose Timer (GPT)- J9 L, X# k3 |
Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution: {7 B, \6 E6 A: u
* J7 }' W" k! v' V- f8 c2 u3 o4 \
General Purpose Wake-Up (GPWU)) e! E4 f Q4 t/ F
All General Purpose Input pins can be configured to generate interrupts or wake-up event.+ B7 g- \1 t+ y0 Y# k
- c+ w! {2 x4 {9 U; j, XGeneral Purpose Input/Output (GPIO)" }: H8 H% K0 v d& P
All I/O pins are bi-direction and configurable
7 o7 _# R' G; f! q5 R" c) O1 N8 y All outputs can be optionally tri-stated) T+ G/ ^0 x; B' @
All inputs equipped with pull-up, high/low active, edge/level trigger selection
. w4 L8 T. X3 J+ T6 ~! S E4 T0 R All GPIO pins are bi-direction, input and output.9 L! ~! r5 q9 t; K
Max. 43 GPIOs/ i2 u4 @. b X. F+ c! w
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Power Management
$ @6 {& W: {* V5 Z8 E Sleep State: 8051 Program Counter (PC) stopped2 m) C( E3 x0 U# g& o) Z( S b
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.8 a% y7 E! E9 k0 q2 K
. {- t2 C. ]8 D* g* B* yTotal Pages: 40 |
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