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Feature Summary$ r; v' F" h8 y; i
' o* g& {! x, K/ M, j
Low Pin Count Host Interface (LPC)
; j$ z+ R3 \4 G! ^1 j) p1 ? SIRQ supporting IRQ1, IRQ12, SCI* q4 S H9 H( d
I/O Address Decoding:) \& q- n9 B& k# F
KBC IO Port 60h/64h
5 X# X7 _ r& y7 d Programmable EC IO Port 62h/66h and 68h/6Ch; }" r- U# |$ @: R
Programmable 4-byte Index I/O ports to access internal registers
$ w: m9 s* A! ]0 o) } One Programmable I/O write byte-address decoding+ Q! s5 i" Q' R
# `, j8 M- f, |) \+ V
X-Bus Interface (XBI)
8 F1 K6 a% v! N; W- Q4 [ SPI Flash support, the operation frequency runs at least 50MHz.2 g2 x. N( U' C4 l
Addressable Memory range up to 24MB.& d; r% ~1 ^4 Q8 M
8051 64KB code memory can be mapped into 4 independent 16KB pages.8 ^. _+ R+ a+ a" T3 o1 T2 A4 U
# e5 V V/ Y. _ L0 t6 F
8051 Microprocessor4 }* Z0 z6 w- Y, ]
Industry 8051 Instruction set complaint with 3~5 cycles per instruction.3 G% P8 f: R" Z( {5 \) w
Programmable 8/16/32 MHz clock4 B6 H' f/ x9 p( Z5 a3 ^
Fast instruction fetching from XBI Interface6 a# Q0 E! l, Q& O2 G
128 bytes and 2KB tightly-coupled SRAM$ B$ j" l( ` k' Z3 \- b" q
24 extended interrupt sources.5 ^6 ?) M4 V: C) }0 G) W1 j
Two 16-bit tightly-coupled timer
$ Q. e: ?- d3 n8 F: d% k8 H& C- M& Y+ V. m# r! v9 \" ^1 ^- R# t' E) }0 R
8042 Keyboard Controller* z) [" J ?3 M0 {% l
8 Standard keyboard commands processed by hardware
* L8 V4 K! @4 j* \9 a Each hardware command can be optionally processed by firmware v( Q4 B% A+ _0 V, o! [
8 l% k6 U8 m# E: O. [6 d- GEmbedded Controller (EC)
0 _! \, @4 A: V+ I; d5 g Five EC Standard Commands can be processed by hardware
' `! v1 {! K4 ]: ?; ` ACPI Specification 2.0 compliant
' C6 Q9 ?# `- d5 e) X# t2 w7 x& L9 I% a6 i Support customer command by firmware
f( h( h k$ a Z4 _- D8 e Programmable EC I/O port addressing (default 62h/66h)+ W' R. u# Q* R2 V5 \
9 }' w' N& y- t* B6 n4 n" E6 T
Analog To Digital Converter (ADC)
4 H- A% G; [* k; ?6 F- D$ s/ ?. l 6 built-in ADCs with 8-bit resolution.# f# ~0 n4 d4 C0 N& T% t# z
The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
4 ^9 k% h0 H+ @& ?9 @3 f4 j: J! j1 `5 G% C1 J8 F% y6 W; ^
Pulse Width Modulator (PWM)
8 G* Y/ E! j/ v 5 built-in PWMs
# [; u( a% j, o9 e( Y/ j. [ Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.1 O6 }7 S& W/ @: e4 v0 F) s
Configurable cycle time (up to 1 sec) and duty cycle.
2 f4 i7 o* Q: s4 h. t" }; e) [
! E2 J( v$ U4 I3 lWatchdog Timer (WDT)
/ l- r1 x# L+ |6 ] 32.768KHz input clock with 20-bit time scale.! v/ q \" @5 w9 {$ ~" I4 K7 `3 i" i
8-bit watchdog timer interrupt and reset setting
- E9 Y) J2 G- l" O D1 V+ c, u
- M/ e {: ^! D$ A% @: d. cGeneral Purpose Timer (GPT)) m5 \% @6 O, D
Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
8 f5 P% j( S6 m3 {! w5 m/ i' W. Q% x" a* a/ F7 A' A, p
General Purpose Wake-Up (GPWU)3 \+ r% W; p& i* D | p& T! _6 ~
All General Purpose Input pins can be configured to generate interrupts or wake-up event.% R s" e. P J% J( |
! ?! w+ Z3 Y, h+ [' rGeneral Purpose Input/Output (GPIO)" X9 c$ [. e) B# q* j
All I/O pins are bi-direction and configurable9 Z9 _5 J* {6 F% \3 c" I+ f2 ^
All outputs can be optionally tri-stated
7 o7 U1 b$ v# m% C. D. \ All inputs equipped with pull-up, high/low active, edge/level trigger selection
0 D7 I- K5 E# g5 H All GPIO pins are bi-direction, input and output.. k% a# _$ Q# d2 g
Max. 43 GPIOs
! `# B7 j; S% k0 y$ m9 t0 U. p' H" M' r/ N% P# B
Power Management
6 w& L% p- T+ Q% g& i- W" V0 O; h Sleep State: 8051 Program Counter (PC) stopped2 p! p/ ~/ S% X& I8 o) f0 \ s7 p
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.* s+ ?; j' ?3 K
. T! i E1 k# G' K& X& ?1 tTotal Pages: 40 |
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