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Feature Summary2 H# w6 F* ^7 b8 P
- y5 f- f$ x6 t8 E. Q7 hLow Pin Count Host Interface (LPC)% T$ F* X0 ?3 b* Z3 A
SIRQ supporting IRQ1, IRQ12, SCI
6 I; y+ v$ [$ a) W2 x, \1 @! I# ^6 A- B5 C I/O Address Decoding:$ S) {" ?2 P7 F: R6 q; m; p1 H0 Y+ d
KBC IO Port 60h/64h& j: A! e+ D5 v' |) l. m
Programmable EC IO Port 62h/66h and 68h/6Ch
" b' }# F# {" v( `0 c Programmable 4-byte Index I/O ports to access internal registers, N& B3 X6 k/ s3 L2 P6 }- y7 e' h0 r
One Programmable I/O write byte-address decoding+ z O+ o' V7 h. r0 O$ n# Q
! k8 }( \7 b) \6 nX-Bus Interface (XBI)$ o4 W- P4 z1 V+ Q5 t
SPI Flash support, the operation frequency runs at least 50MHz.
2 T3 `0 r+ d- p2 p' ?4 p0 |# [. T Addressable Memory range up to 24MB.
) @% d5 x; `( U g; x- l. O# q 8051 64KB code memory can be mapped into 4 independent 16KB pages.
5 y, ^& ^; D& R b. S2 n, j
/ U' q, N' {* K2 E8051 Microprocessor: k/ L& k0 y' _! q3 b
Industry 8051 Instruction set complaint with 3~5 cycles per instruction.. O& j6 V0 V! F2 C' g* m
Programmable 8/16/32 MHz clock
" \/ m5 ?% ^: N7 Y Fast instruction fetching from XBI Interface
% [, L' a5 z6 S, l9 W3 Y 128 bytes and 2KB tightly-coupled SRAM
3 V& [6 S, C4 W 24 extended interrupt sources.% O/ c9 x# @# L8 p7 p4 N
Two 16-bit tightly-coupled timer
6 {' v7 w$ H" E. A2 o& R
9 R& Z6 }+ p3 O6 t+ @& z8042 Keyboard Controller
- B! m5 ]- U* C/ r& A 8 Standard keyboard commands processed by hardware# J9 P" z8 @9 C5 L. u: N; o4 _8 @& [
Each hardware command can be optionally processed by firmware
3 U' k2 X' x" z- a7 [
8 a0 T6 E3 G* C8 X+ xEmbedded Controller (EC)
7 t( Z# }; m2 p Five EC Standard Commands can be processed by hardware
+ n! p h4 P2 } ACPI Specification 2.0 compliant
4 z8 m3 {5 i. ~ Support customer command by firmware
) P: {: J; L; c+ p Programmable EC I/O port addressing (default 62h/66h)
0 K K4 V$ U. j( u3 y1 i6 ?, X, i/ e# K( ?3 G& h
Analog To Digital Converter (ADC)
p1 H+ L$ k1 ]2 x' P 6 built-in ADCs with 8-bit resolution.
" t( g% [' P9 P( N- o4 \" g/ g The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
6 U7 v8 ]. d2 E5 f4 I- T# }8 g! n5 ]
Pulse Width Modulator (PWM)
* H7 k' P$ q; s: Y6 z+ j 5 built-in PWMs
P1 f& X8 B1 y7 R# `2 m Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.
, T, Y' }" v! b* S- _2 B Configurable cycle time (up to 1 sec) and duty cycle.1 b7 }3 g" ]4 G) g) i
& O6 L3 t& E. Q+ ^: T# w, a
Watchdog Timer (WDT)
( a; s. c6 r d2 Q* S! |7 V 32.768KHz input clock with 20-bit time scale.
3 U# k" t. c1 N: K3 D* M 8-bit watchdog timer interrupt and reset setting% G+ Y7 q3 l$ X
" I: T& _# v! K# J3 i) o2 @* b
General Purpose Timer (GPT)/ g% h% x) D- I* v. U
Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
- [% K3 ~8 h2 ?9 Y' o3 E
; b4 _0 |. [) y* WGeneral Purpose Wake-Up (GPWU)* @% g l7 ?; C4 S s
All General Purpose Input pins can be configured to generate interrupts or wake-up event.+ O# R3 ]5 @0 E) l- W
) }/ ~1 m5 d- k3 s
General Purpose Input/Output (GPIO)
% C5 g! e0 B& ]9 }7 i. | All I/O pins are bi-direction and configurable
$ F/ R8 Z# u1 P All outputs can be optionally tri-stated
8 \/ l) s: N( j8 R$ q5 t All inputs equipped with pull-up, high/low active, edge/level trigger selection
+ W) c9 \' x5 G6 {# m All GPIO pins are bi-direction, input and output.
) D* b9 N# ]$ Y0 V Max. 43 GPIOs
: {- S8 `2 U! @0 n8 W$ {
+ h, w4 q% {! N2 F9 R8 @Power Management
0 I+ n2 I4 v0 T Sleep State: 8051 Program Counter (PC) stopped* p; B' l }5 e! v+ J. E
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.$ r3 o% w. L' A& r' W4 x
I+ {* Z* ~3 J2 C" {Total Pages: 40 |
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