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Feature Summary$ c( I3 Z- _6 P' m L; i) `8 L. n0 n
0 J3 {9 p' i( [- ]% M% _Low Pin Count Host Interface (LPC)5 W0 I' v+ k1 s, A& w5 r
SIRQ supporting IRQ1, IRQ12, SCI
; w! \/ b; O0 y; B8 ? I/O Address Decoding:6 N+ z$ b& H" k6 O0 ^
KBC IO Port 60h/64h
2 O- ?! r! B3 Q5 J$ Q! z' h- _ Programmable EC IO Port 62h/66h and 68h/6Ch! H$ H! u) b* m
Programmable 4-byte Index I/O ports to access internal registers; Q/ E+ H( c1 J* B
One Programmable I/O write byte-address decoding
" x3 K8 x6 ]0 `0 V" M( v) ^
8 l7 Q S, ]. i1 W( `1 S9 U/ x( z0 ZX-Bus Interface (XBI)
8 ?2 u/ ^: W% z+ W: u# y6 u: b SPI Flash support, the operation frequency runs at least 50MHz.
# I. s* X; L& u T$ `& _ Addressable Memory range up to 24MB.
" A6 ^" l& s9 j, K( _ 8051 64KB code memory can be mapped into 4 independent 16KB pages.
' z/ G2 N7 a2 t) m
' r' P& l" c- B/ M8051 Microprocessor* D {& U; G o1 ]& g1 f
Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
3 u0 x8 V/ [( g$ H4 Q1 p6 v Programmable 8/16/32 MHz clock& q5 D; i4 B9 A% _6 Z/ y5 E5 `
Fast instruction fetching from XBI Interface2 W9 s% _4 W5 q A) a+ R
128 bytes and 2KB tightly-coupled SRAM
) ~) {* N% }* U, E6 V 24 extended interrupt sources.
$ I# C: B) c, e7 B% n4 P a( w( n Two 16-bit tightly-coupled timer
! ^: F! s7 e5 A" f, F, u0 O! a. \* O7 |& G6 P: Y8 E9 F+ I
8042 Keyboard Controller
3 r5 r+ @- ?; p 8 Standard keyboard commands processed by hardware
' J- ^2 y$ O& I/ ^ j Each hardware command can be optionally processed by firmware
8 |& F6 W2 m, p/ z8 T3 V5 v) o4 f' A7 b. z! v
Embedded Controller (EC)
+ a5 D# L+ J/ _- i$ @ ?( q# K Five EC Standard Commands can be processed by hardware
( k- M" y0 ^" ^6 T- V" K, Z ACPI Specification 2.0 compliant' M, q. t: v0 _2 x+ k" X
Support customer command by firmware
- A! l, m% n" g4 V, t Programmable EC I/O port addressing (default 62h/66h)
8 X8 d* {$ X! L, o/ {2 C! `, c* ~0 w1 o
Analog To Digital Converter (ADC)& U r7 V" A8 c, R% n
6 built-in ADCs with 8-bit resolution.
+ _ u' H3 }% [, E# ^6 U2 c7 A- W" C The ADC pins can be alternatively configured as General Purpose Inputs (GPI).1 _) H g2 @. _. I0 ?4 ]) Y
4 e% Y" [% i7 N- I* w. d
Pulse Width Modulator (PWM)0 R2 [5 R, ^, [7 X% `! |
5 built-in PWMs6 i, [& E* h4 F0 Z' q; Z& E
Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.' [* C/ F, p. a; |" V' S$ t
Configurable cycle time (up to 1 sec) and duty cycle.+ }- U0 I" q L3 F) M5 H1 W9 \
+ B& y5 a7 M; B7 v; C
Watchdog Timer (WDT)- n3 z. ]4 w. G: {2 T% m, C% E
32.768KHz input clock with 20-bit time scale.
+ b C+ E9 [3 S. W 8-bit watchdog timer interrupt and reset setting8 F. u" z) T- E5 Y1 j
1 c1 N7 h- ~! W# W. j0 L& w4 I
General Purpose Timer (GPT)
8 `/ A2 A2 ?8 @0 y" A8 o/ {3 j Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution4 j4 Z5 a! J8 N) Q" y
2 g6 ]& p C9 h8 V2 o: UGeneral Purpose Wake-Up (GPWU)
6 c4 n, j; L4 U9 r5 }) [6 E; h* B All General Purpose Input pins can be configured to generate interrupts or wake-up event.; M) y# r5 ]. ^3 L! V- ^
6 C* L1 |/ M6 U8 \7 a- K2 KGeneral Purpose Input/Output (GPIO)
8 C5 z: r6 T, ^ All I/O pins are bi-direction and configurable7 U6 s3 Q1 c4 Y, x7 H3 T
All outputs can be optionally tri-stated4 D, Y# @! q! V1 k. E0 ~. @7 w
All inputs equipped with pull-up, high/low active, edge/level trigger selection
# z3 X% Q9 k& Y All GPIO pins are bi-direction, input and output.5 |- H* ?: \& u; } i
Max. 43 GPIOs
4 H3 Z, V! ^% z( ~& Y; N% r
0 H( q' L# K6 H7 c, ?7 ~+ C1 APower Management
- J q/ ]' V% p/ W7 {# U1 ~- j Sleep State: 8051 Program Counter (PC) stopped
4 K' y+ R+ N h/ @ q% { Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA./ l7 W* N2 _( e3 p# Y. i' b
% R, Y& b, C. x' YTotal Pages: 40 |
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