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Feature Summary
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' f, X8 F: s. q: v6 ?Low Pin Count Host Interface (LPC)4 K! q: K1 \# Z1 N" e; t1 `0 h
SIRQ supporting IRQ1, IRQ12, SCI
$ ]! q5 p; r: ?' Q I/O Address Decoding:
Y, o! V Z& A. C. Z$ {- r KBC IO Port 60h/64h
" z. Z8 d2 p7 m- b6 J$ N" p Programmable EC IO Port 62h/66h and 68h/6Ch
2 O- M& a5 N* ^/ E+ O; y3 c3 Y Programmable 4-byte Index I/O ports to access internal registers8 G8 [" S3 m) h& j3 }
One Programmable I/O write byte-address decoding
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X-Bus Interface (XBI)$ k; l( r( R( c; x h
SPI Flash support, the operation frequency runs at least 50MHz.
/ `! z6 q, O9 N4 T- B Addressable Memory range up to 24MB.
$ k% {: z3 O7 X( \+ Z 8051 64KB code memory can be mapped into 4 independent 16KB pages.
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5 U* R4 C) g/ K$ B6 y4 c+ k8051 Microprocessor& p3 @8 F% l4 k
Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
" C% ^7 A1 H% ]8 } Programmable 8/16/32 MHz clock
/ _: x0 a% H0 i: V; ~) `( q Fast instruction fetching from XBI Interface
! O' N. R! @, [1 i 128 bytes and 2KB tightly-coupled SRAM. Q, ~/ ]. R6 d3 W8 d5 L, b
24 extended interrupt sources.. C- r; m+ G+ u
Two 16-bit tightly-coupled timer
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8042 Keyboard Controller9 W- \0 _6 M8 U' X- |0 g- k
8 Standard keyboard commands processed by hardware4 b. D( J, H7 M2 z1 D% h% |
Each hardware command can be optionally processed by firmware7 x. a/ n) [; [5 B
& k a/ t6 k: e% v2 F9 V. wEmbedded Controller (EC)
* Q3 b; D- X; |' r- E Five EC Standard Commands can be processed by hardware. t; P& `- h! ]# m: h3 s8 l" G0 K' k
ACPI Specification 2.0 compliant
0 c( B$ r0 y8 v# x0 j Support customer command by firmware
; O3 [; M3 f% L" p' h5 x Programmable EC I/O port addressing (default 62h/66h)
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' T1 ^; m. F) y; V+ xAnalog To Digital Converter (ADC)
0 w* I+ ` b9 j9 l+ c 6 built-in ADCs with 8-bit resolution.( v- {% \* K J) L6 H
The ADC pins can be alternatively configured as General Purpose Inputs (GPI).% a2 Z# Q, F7 F9 h4 @- y' l
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Pulse Width Modulator (PWM)7 {* \2 [/ x) O D; [
5 built-in PWMs- X- i! u3 r- \. C
Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.$ K$ B3 b$ [5 U/ j
Configurable cycle time (up to 1 sec) and duty cycle.. _$ F5 G. m/ y, [$ ]
' {7 a; I) u' z) j+ S4 N" aWatchdog Timer (WDT)
f3 o0 u" ] J7 p" x. E 32.768KHz input clock with 20-bit time scale./ J# N7 x4 S5 @/ B7 [/ z+ e% q- x
8-bit watchdog timer interrupt and reset setting
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! O& u* {5 d) L" z9 mGeneral Purpose Timer (GPT)
3 G5 `! r$ L8 |: Y7 Y Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution. J3 ~9 t4 a/ u. U" N
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General Purpose Wake-Up (GPWU)* ]& U$ h0 a d8 d* g. L" A2 l
All General Purpose Input pins can be configured to generate interrupts or wake-up event.
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8 \3 F8 Q8 T' L6 ^1 A+ lGeneral Purpose Input/Output (GPIO)/ j) Q/ P% H5 z4 X+ }
All I/O pins are bi-direction and configurable6 Q) X0 d+ T. x8 `
All outputs can be optionally tri-stated
8 r( G0 j2 a% B9 S4 V0 B All inputs equipped with pull-up, high/low active, edge/level trigger selection- f B6 D7 F p! q! Q
All GPIO pins are bi-direction, input and output.9 [* |" o4 G8 G, t" r' A
Max. 43 GPIOs
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9 Y8 Y. \# l: a, V8 c+ ?4 DPower Management2 X( P% `, m7 x* k) R! @- v, H
Sleep State: 8051 Program Counter (PC) stopped! _6 ^3 R8 w3 r
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
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