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Programming Interface for Bus Master IDE Controller Revision 1.0; i9 G4 n* d+ ^& c$ i9 R( [; T
1994/05/166 m. X4 x6 Y; A: A+ S# W2 H
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk0 ]$ t8 U5 C. I; s4 p& m- }' y
controller that directly moves data between IDE devices and main memory. By performing the IDE data! L" h% F* W N5 e5 ]: a H
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
& w6 O, m( A, J4 wand improves system performance in multitasking environments.
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Until this specification is ratified, it is solely" e' {1 h; O" ~0 s4 T
owned and maintained by:) W- A0 W o; q4 A: C; `+ g. H
Brad Hosler, Intel Corporation6 l/ p) ^( M1 v" d* S
bwh@salem.intel.com (please comment using email)3 v o: o S( X+ ~$ c% q
503-696-8431 |
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发表于 2010-7-14 14:53:56
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