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Programming Interface for Bus Master IDE Controller Revision 1.0
}( }- @0 Q6 L d. H0 {1994/05/16 J" j# C+ u- v/ u
|5 q0 d& ^8 l( G% v( sThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk# Q+ W) x/ H& R0 `9 ]
controller that directly moves data between IDE devices and main memory. By performing the IDE data9 D$ Z. }, g2 @3 \4 x) k
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)7 A7 F3 I( ^6 ?# F0 \
and improves system performance in multitasking environments.& L, E2 o4 B/ i7 |. r
2 U7 h; B4 O6 f' f- s& _6 L0 x# nUntil this specification is ratified, it is solely
2 A3 F: r8 E% b) g& H" I6 `owned and maintained by:# \% ], B, |" N( v4 B& @, o! y
Brad Hosler, Intel Corporation
! j3 j) j1 @' y' J' l- I' ]bwh@salem.intel.com (please comment using email)9 A- t" X' i5 O$ i# D' D# c
503-696-8431 |
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发表于 2010-7-14 14:53:56
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