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Programming Interface for Bus Master IDE Controller Revision 1.0
* @4 s) Y2 L/ Q9 D- n$ D1 V6 w1994/05/16" }7 ], i4 [8 R/ k! E6 T0 v
: |. @! a5 w' y) }% yThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk7 V. Y& c$ `8 O3 @7 }
controller that directly moves data between IDE devices and main memory. By performing the IDE data* t o4 M) C9 x/ Q4 h7 L3 l+ H
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)3 O! [- Y. M' f9 ^! T% U& s
and improves system performance in multitasking environments.8 l0 Z* `" d- F' l$ q
$ C) N( j8 U; ]! q: W* cUntil this specification is ratified, it is solely
* W+ x, R) ?1 w( v- X% U: downed and maintained by:4 y6 K5 y& e: E
Brad Hosler, Intel Corporation! B0 L/ O8 C* ?2 v6 p5 p
bwh@salem.intel.com (please comment using email)* V U x/ i! M% `) h1 C5 }
503-696-8431 |
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发表于 2010-7-14 14:53:56
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