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Programming Interface for Bus Master IDE Controller Revision 1.0
p# K! e0 A8 }: v0 l8 _) k1994/05/16" e% ^" {- d' a! h0 W3 K- N
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk* ^ P/ q5 Q' i2 B0 P
controller that directly moves data between IDE devices and main memory. By performing the IDE data
, }. R3 M, x) w; T. Z# U( c7 Utransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
$ d4 N! O& t% Z" }and improves system performance in multitasking environments." l6 }8 O- f9 L) b
$ c: s" ?# `' l* g8 WUntil this specification is ratified, it is solely- k% V! s0 Q+ Y8 Y* M. W3 n
owned and maintained by:) d, z3 e! f& m+ S4 I
Brad Hosler, Intel Corporation
8 k* J& i4 F# l; {bwh@salem.intel.com (please comment using email)7 u. u& g3 | h; Y0 w/ J/ x/ g
503-696-8431 |
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发表于 2010-7-14 14:53:56
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