Programming Interface for Bus Master IDE Controller Revision 1.0

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Programming Interface for Bus Master IDE Controller Revision 1.0
1994/05/16
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: ~5 V3 E0 O% |: ]! R1 }This document defines a register level programming interface for a bus master ATA compatible (IDE) disk
" j9 L/ t5 Y: Z' R; Zcontroller that directly moves data between IDE devices and main memory. By performing the IDE data
* K/ ]9 v. F$ s: Ytransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
& ]9 V1 m7 w) O( P; }! u4 k, a2 ]( Land improves system performance in multitasking environments.
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: F/ t/ o% Z- F) xUntil this specification is ratified, it is solely
owned and maintained by:
Brad Hosler, Intel Corporation
6 A7 N6 E4 G5 W$ P# K* k8 y2 Ibwh@salem.intel.com (please comment using email)
503-696-8431