|
|
Feature Summary
5 _9 i* r: ]( _0 K. V- U+ o" h, Y4 L `/ X
Low Pin Count Host Interface (LPC): [( t0 ]; A, o1 }, d0 M) q9 ^
SIRQ supporting IRQ1, IRQ12, SCI: `8 q" [: s2 `8 F
I/O Address Decoding:$ {) _2 F" x8 P; |) ]! @
KBC IO Port 60h/64h
$ M0 K5 E, @; F' r" w- [4 _ Programmable EC IO Port 62h/66h and 68h/6Ch5 l0 W3 t1 x; E: i. ?8 l
Programmable 4-byte Index I/O ports to access internal registers! H; P ^7 F9 `; L r* M- R
One Programmable I/O write byte-address decoding
$ f2 h8 w# U7 z& M7 ?
" X, o# B8 m9 [X-Bus Interface (XBI)
% K$ U/ }2 I6 U2 \ SPI Flash support, the operation frequency runs at least 50MHz.5 o) H5 N$ V7 t6 ^
Addressable Memory range up to 24MB.
4 q# P `+ l$ r2 d( u 8051 64KB code memory can be mapped into 4 independent 16KB pages.7 T% j$ {! k, r, E& d) Y. L7 n
0 Z" p5 w1 k2 }' p; Y
8051 Microprocessor
0 `0 _. _% ], d/ L" P/ B1 s$ ?# j Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
' y' U+ i4 U. e9 K+ h Programmable 8/16/32 MHz clock0 X( M7 K: R! T1 H1 V
Fast instruction fetching from XBI Interface
( s) k. L% {( o 128 bytes and 2KB tightly-coupled SRAM
! R U0 m. |, p+ o 24 extended interrupt sources.
4 k1 ^4 W) U2 A& Z Two 16-bit tightly-coupled timer
; V7 b$ {+ s I7 L2 H( `; w4 ^8 ]5 t1 n* g
8042 Keyboard Controller" V3 g3 s# R! Y/ z0 [
8 Standard keyboard commands processed by hardware
/ u: d5 O+ ^4 w7 O Each hardware command can be optionally processed by firmware
; I$ `$ J' G' o6 R/ u w6 J( S o! L r1 N: ]8 [
Embedded Controller (EC)0 N' M" H9 J/ I0 A
Five EC Standard Commands can be processed by hardware
9 |- z' Q: R, g ACPI Specification 2.0 compliant) y* j( w- n* d( h9 a6 ]! T
Support customer command by firmware3 o* H, k1 H# B4 q R
Programmable EC I/O port addressing (default 62h/66h)( K. V9 [& T/ ~7 B4 ~ i0 `- j7 M! r
* Y( r- W$ O+ c9 j" U' T |% V
Analog To Digital Converter (ADC)( g, B. p5 [" W9 h d3 h; Z, E
6 built-in ADCs with 8-bit resolution.. `# w9 i& R$ m- W$ O
The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
( m; R5 k8 c1 I2 J- p
* b9 n9 n; V, iPulse Width Modulator (PWM)9 t. R0 {+ ~' z. `: @
5 built-in PWMs
) p/ X4 s5 w2 D Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.# Y, \" Z% k5 b) w
Configurable cycle time (up to 1 sec) and duty cycle.# G3 J: ]0 r# X! T
9 v8 c% q" X- ?- `1 L+ y+ l( K
Watchdog Timer (WDT)
& \: k7 m0 h4 R% L6 a 32.768KHz input clock with 20-bit time scale.
' ]1 k/ W) N+ q" ]! I$ T5 N O' N 8-bit watchdog timer interrupt and reset setting9 c; ?- ]* i! M. g- L. k
" o+ K* D0 ^. v. AGeneral Purpose Timer (GPT)9 I* M5 G$ U2 W. @) a& Q
Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
2 o/ H) @" c/ Q+ g3 h5 V
9 ^1 h' L, j# lGeneral Purpose Wake-Up (GPWU)
, _+ ~5 m2 x+ \- R0 a& ^1 y0 L All General Purpose Input pins can be configured to generate interrupts or wake-up event.
( z; ~* R1 V4 R8 \) {& @7 N* a0 H0 F/ M
General Purpose Input/Output (GPIO)* O% S& J/ o# ^" q
All I/O pins are bi-direction and configurable8 m: F# H- j' A6 x" |; h' S! G
All outputs can be optionally tri-stated- L- x9 u! u( m
All inputs equipped with pull-up, high/low active, edge/level trigger selection
! S* ?9 X, K& ^) ^ All GPIO pins are bi-direction, input and output.
, f( W- N/ @4 K! m; n Max. 43 GPIOs' T( d2 m9 O& O" \
3 u6 c! }% M5 R$ b: E1 M6 ePower Management
2 V( I; h$ C# d) L) D Sleep State: 8051 Program Counter (PC) stopped
8 p4 S$ G* i+ F5 L. N; w4 m" K Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
1 K& `- S* u: i% Z* `* u" M; @2 c
% [( @6 N3 b5 BTotal Pages: 40 |
本帖子中包含更多资源
您需要 登录 才可以下载或查看,没有账号?加入计匠网
×
|