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Feature Summary
1 r' e' I- {- n% L$ _" t4 _& n/ H0 B8 e: ~6 O+ [
Low Pin Count Host Interface (LPC)& t/ K7 H; V; s& C
SIRQ supporting IRQ1, IRQ12, SCI& ^; E+ Z3 c! n1 Z+ L6 @
I/O Address Decoding:
& M0 l- G z. A. P' I7 ~ KBC IO Port 60h/64h
( N( ^" J/ l: v9 c4 u! d! b Programmable EC IO Port 62h/66h and 68h/6Ch2 d- {- q2 E! p; I) ^1 [! s; x
Programmable 4-byte Index I/O ports to access internal registers7 C7 X+ O+ |: p. T6 _5 ^0 {1 S& h4 L
One Programmable I/O write byte-address decoding
, m+ I3 w+ j/ `, d: Y4 e/ A' [
, I* x( T( X0 FX-Bus Interface (XBI)" s! Q! p9 ~4 C. n& h9 H
SPI Flash support, the operation frequency runs at least 50MHz.
; x; u- U C8 H Addressable Memory range up to 24MB.6 i" ^2 n4 \0 l( S
8051 64KB code memory can be mapped into 4 independent 16KB pages.% ^0 j' A, c5 q( ?1 L, e
e8 E! L! n% h
8051 Microprocessor4 }. H4 W$ t# y( k# y( k& F
Industry 8051 Instruction set complaint with 3~5 cycles per instruction.# h2 @$ a% _/ y1 j7 W7 c, M
Programmable 8/16/32 MHz clock4 O* s; }$ Y4 k+ @+ [7 I
Fast instruction fetching from XBI Interface/ }0 t6 ]# T& ?, H1 v! ^) Z
128 bytes and 2KB tightly-coupled SRAM
0 ~8 C/ T3 B3 p. ~' g 24 extended interrupt sources.
: g5 c, ^! t2 u6 \" I& j4 U Two 16-bit tightly-coupled timer. } C! W9 \) m6 T+ l7 p( ~' Q
: D3 c) v3 x; h* \
8042 Keyboard Controller
0 R3 l u! b' O1 P3 X9 \3 i 8 Standard keyboard commands processed by hardware
+ P1 Z3 s* p. v* j+ Z' f Each hardware command can be optionally processed by firmware3 w% ]/ X' x+ {. a
: S3 V4 {& }, X2 z5 u
Embedded Controller (EC)' h$ d0 V' G9 o L& h
Five EC Standard Commands can be processed by hardware# \8 I. D, S3 J6 ?) Q" Z: M
ACPI Specification 2.0 compliant
$ D$ Z. S7 P7 p3 o$ ?- @ Support customer command by firmware3 B4 K5 h, d5 `& P$ B
Programmable EC I/O port addressing (default 62h/66h)' W8 w8 I4 M3 A
" i3 { V" U9 e9 U
Analog To Digital Converter (ADC)
# F0 ?2 b8 v) C0 N: H8 [ 6 built-in ADCs with 8-bit resolution.
6 T- j% ]0 \0 C c2 T7 w i, O" Q The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
% r) y' ?; |' J. @2 [& D' ?9 m9 a8 R' _
Pulse Width Modulator (PWM)
% v" ^" _# ]9 W, K7 x3 D 5 built-in PWMs4 G' U( _3 D9 a
Selectable clock sources: 1MHz/64KHz/4KHz/256Hz." B; ^% O- _, K: @
Configurable cycle time (up to 1 sec) and duty cycle.) _; e/ G+ E( N* `, }
) D6 f0 W' T qWatchdog Timer (WDT); Z: J7 u* }% I
32.768KHz input clock with 20-bit time scale.
% O% ~/ t7 D8 w* I7 a7 V 8-bit watchdog timer interrupt and reset setting
v d9 I8 P. o8 ?1 e' R4 Z1 x4 b- G$ }! v' T! U: E
General Purpose Timer (GPT)6 v* U5 D, }- W; h
Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution6 q- r" \3 }9 G0 R J
/ t E1 Y- v, {General Purpose Wake-Up (GPWU)
: T* m5 o9 w s4 d All General Purpose Input pins can be configured to generate interrupts or wake-up event.
- I8 q' P+ @+ X( d3 p( ?; ? _. j$ P. a
General Purpose Input/Output (GPIO)& j7 X, a& `, r; ~, e
All I/O pins are bi-direction and configurable4 A0 f+ Q# O7 [; m
All outputs can be optionally tri-stated- o: w! E; E F* Q6 a, A. n
All inputs equipped with pull-up, high/low active, edge/level trigger selection( W, S- G% U: C- E0 Q
All GPIO pins are bi-direction, input and output.
+ c/ L* Q; A: O/ `- I& K, s Max. 43 GPIOs+ S2 L/ Y3 G8 L/ U) Q/ j
! e3 @. k1 h: S- N8 X
Power Management6 f$ t* x0 @+ R6 [+ G
Sleep State: 8051 Program Counter (PC) stopped
2 E) {8 J' m& T8 R; Z5 l3 c Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.; |! i" f) f, y1 _, }/ J0 |9 }& a
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