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Feature Summary! T4 q" u6 E" F- D2 n& @
% N! i: s, Y. q7 ]Low Pin Count Host Interface (LPC)
/ Y2 I/ J; }4 q$ s4 z$ p- @ SIRQ supporting IRQ1, IRQ12, SCI# E; m+ i1 t, t% |" M( l! k
I/O Address Decoding:9 N5 b# O* m6 e6 E( J/ p
KBC IO Port 60h/64h
" f% U" m9 U7 j Programmable EC IO Port 62h/66h and 68h/6Ch
. s4 C, a8 Y. s$ V3 C! W Programmable 4-byte Index I/O ports to access internal registers
4 O+ G" L% q) R& H1 v; q$ |4 I" s One Programmable I/O write byte-address decoding% u1 S# q' w& ?/ ^% C( @0 Q
* A3 V" U/ {" [! JX-Bus Interface (XBI)
# [$ {" F2 N, F* A0 ] SPI Flash support, the operation frequency runs at least 50MHz.
6 W* G. w( ?( ^* z Addressable Memory range up to 24MB.& K, K' q* o7 ^ o: Z: Y
8051 64KB code memory can be mapped into 4 independent 16KB pages.; ^9 K+ [0 c. I" d- N
- k2 g6 g \" x1 I6 k) z8051 Microprocessor
6 N: c: i; P7 M Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
* k" J1 K% [9 |3 e8 `% X, g) h( j Programmable 8/16/32 MHz clock" f0 n% P1 _. ?# d
Fast instruction fetching from XBI Interface' M1 D; b7 Z& G+ m
128 bytes and 2KB tightly-coupled SRAM+ {/ O; M( x/ O
24 extended interrupt sources.
* z {8 i( W( p* j, \; ~ Two 16-bit tightly-coupled timer9 e* `) X4 O/ N/ {" C$ [
) i; v$ v; n4 G+ c8 L$ {2 m4 K: V: O8042 Keyboard Controller
% b$ m9 {7 z( G9 f" \ 8 Standard keyboard commands processed by hardware @! ]0 A& W- z. A: f# l
Each hardware command can be optionally processed by firmware) H- W. D% _4 ?7 I3 B
# [7 h( i }- D0 e LEmbedded Controller (EC)0 m6 i2 a0 m% G4 P+ T. N6 y
Five EC Standard Commands can be processed by hardware& q# A# A' m# X* K3 z% p4 i' b
ACPI Specification 2.0 compliant1 ~9 `, h; }7 n
Support customer command by firmware* ]) j, g: D. b
Programmable EC I/O port addressing (default 62h/66h)6 K, |# b( |* d# L/ i# t
- f( Q$ g* m0 ? k
Analog To Digital Converter (ADC)
) r o3 h1 q D% f" Q 6 built-in ADCs with 8-bit resolution.
' F3 t, j6 ?/ U6 ^% H' ?3 G The ADC pins can be alternatively configured as General Purpose Inputs (GPI).2 }: a. {! x& t( X# X
3 V; P1 Q: G) O: U
Pulse Width Modulator (PWM)
+ ? I& F0 D2 W2 _; R M) ~ 5 built-in PWMs4 e; B2 [ {5 s& X. K- [; B6 ^/ q
Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.& T! ~& F# y, J$ A% R
Configurable cycle time (up to 1 sec) and duty cycle. Y/ M9 M: e% B( G
. i# j2 F4 b f$ {. o8 ?
Watchdog Timer (WDT)
6 c9 s. p9 S$ h$ l" t( i 32.768KHz input clock with 20-bit time scale.- K$ S1 v) Y+ ^5 V
8-bit watchdog timer interrupt and reset setting
! | W" f9 T/ T5 O2 x. e/ T
8 K; }# i E3 w% Y8 d; H( SGeneral Purpose Timer (GPT)
) M$ e: [4 P3 b# W/ a Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution" h+ r% @9 G, e, | y8 L" H
# l3 c: J0 L: ~# O; B* t% EGeneral Purpose Wake-Up (GPWU)# z0 E8 _* j4 ~* b
All General Purpose Input pins can be configured to generate interrupts or wake-up event." ]# n* j) T N- u
( L! ^4 {1 f$ jGeneral Purpose Input/Output (GPIO)
. {+ K3 j2 W2 a6 z All I/O pins are bi-direction and configurable# [! P1 I. x. _$ B: u9 l. {3 \6 R6 Q
All outputs can be optionally tri-stated, E/ w c% K' S4 r- n/ u
All inputs equipped with pull-up, high/low active, edge/level trigger selection
8 {+ |7 \- b+ x9 D/ k All GPIO pins are bi-direction, input and output.
0 ^7 W/ r) [" Q$ a6 {" d' w/ J" n Max. 43 GPIOs
, r% q4 T: ]% n5 N) n0 H9 U% K! i1 X4 c& Z8 W
Power Management
" D: o! G/ D. h/ `$ G% h! ] Sleep State: 8051 Program Counter (PC) stopped$ L: g! h: Q2 A6 N0 b
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.5 e1 H: {2 U) D$ d1 K
6 d, T b( }; C) ` c3 {
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