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Feature Summary/ ]+ s' }6 L w" T: S
# u3 K! r- k l
Low Pin Count Host Interface (LPC): O, b6 E+ d$ s# V0 v; Y m2 Q
SIRQ supporting IRQ1, IRQ12, SCI
7 }2 R$ a+ ]! _" D0 j I/O Address Decoding:
* J4 _6 n' I, p$ o" ?1 I KBC IO Port 60h/64h" G% T3 v: g \( U/ ]+ q- p* K
Programmable EC IO Port 62h/66h and 68h/6Ch. c: N2 y1 i- _2 K
Programmable 4-byte Index I/O ports to access internal registers4 w% w3 E: d/ Z. w! }
One Programmable I/O write byte-address decoding5 R# A P! y+ v/ f; d5 V: @ V, M; e+ r
) `+ z7 I* Q% c2 r+ l% \ B
X-Bus Interface (XBI)
. R! K8 [8 b: \) l6 Q3 C1 ]; E0 \ SPI Flash support, the operation frequency runs at least 50MHz.5 H( I- t; [; D o
Addressable Memory range up to 24MB.
@( V6 X: L8 e3 f7 O; | 8051 64KB code memory can be mapped into 4 independent 16KB pages.% P1 l. i T: d; [1 W8 `0 j& F
8 m# {# o. v8 x5 @6 ^! M8051 Microprocessor! Z1 ]+ L4 m6 f: c9 |
Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
9 d2 X0 p% |: |8 p/ a1 i7 `' o Programmable 8/16/32 MHz clock7 y9 r+ e( {4 Y, d1 |
Fast instruction fetching from XBI Interface4 _- l, t" t3 r2 ?% V' C! z
128 bytes and 2KB tightly-coupled SRAM) w M* a9 d. E, P4 L% M
24 extended interrupt sources.
6 P3 I9 W) B+ G0 h) t9 k Two 16-bit tightly-coupled timer/ N: V/ v* U& S. l: x) Y( X0 q
* ]1 K# S0 l5 Q0 P8042 Keyboard Controller# k J! j/ H$ ?) {/ ^ X) Z( C/ ]
8 Standard keyboard commands processed by hardware. J+ H. ?7 n; p1 V
Each hardware command can be optionally processed by firmware
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' J; Q3 R/ y3 E. Z# N1 \5 O/ n# d, WEmbedded Controller (EC)1 E2 w" V M/ E: n G% ]+ W0 j& w
Five EC Standard Commands can be processed by hardware
( B/ {( l5 l1 v ACPI Specification 2.0 compliant+ M! }1 d$ P- U. N1 {! H0 h
Support customer command by firmware
: d$ Z3 p( P/ Q& O. V Programmable EC I/O port addressing (default 62h/66h)
5 |+ p* }9 u! I, k' n* }6 G, ?8 m
Analog To Digital Converter (ADC)
- W; N) M0 f3 {$ j2 M, c 6 built-in ADCs with 8-bit resolution.4 |) y, o& i, F/ w2 f- m" H
The ADC pins can be alternatively configured as General Purpose Inputs (GPI).7 Z) ?& j; H- ]! U9 y9 H
P D8 t2 H; e- J3 a4 k7 t- U
Pulse Width Modulator (PWM)
# L, | t' r; d% T; ] 5 built-in PWMs
8 d( r. r* I4 F6 K3 O6 X( L Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.' Q8 ]( P) o% h) g f8 C2 z
Configurable cycle time (up to 1 sec) and duty cycle.. v2 S" A! e4 R, E
; L0 h. M( d5 b0 [' _# D$ PWatchdog Timer (WDT)
: E( V+ `/ T @5 t+ E3 d6 N4 n 32.768KHz input clock with 20-bit time scale.+ P. O1 Q1 Z7 Q
8-bit watchdog timer interrupt and reset setting6 Y% J. @7 g( W- q7 X
7 H: N' |" g' ?, A8 f
General Purpose Timer (GPT)
: J" i- j% [4 e Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
( g' v+ `: R; \/ I0 G F% L- t) l) |( z8 i- ~* H0 c" j2 O+ T
General Purpose Wake-Up (GPWU)
, w1 x Q/ h& n1 T9 t# G/ ]" t All General Purpose Input pins can be configured to generate interrupts or wake-up event.
; E V R6 [3 u& e* U+ t9 s+ p, j& V
General Purpose Input/Output (GPIO)/ ]. p5 F# h5 W! w& c, K# S
All I/O pins are bi-direction and configurable
$ i, U; W% H% |* S All outputs can be optionally tri-stated
% V9 x3 \: l$ c/ T& n0 ]2 M All inputs equipped with pull-up, high/low active, edge/level trigger selection
5 [0 Q! q+ g+ M* T All GPIO pins are bi-direction, input and output.
/ l# `5 B) g) p2 ] Max. 43 GPIOs7 @8 ?2 Y2 {; y& i5 D% Q" N s
% G" P+ Y( B: o* s
Power Management: @% h) r2 @6 i. P# R
Sleep State: 8051 Program Counter (PC) stopped
/ I: [5 ? A' S# L4 F/ O Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.3 d; ^* U/ K% r0 o5 }
. T+ b9 g! m7 l3 {3 G0 OTotal Pages: 40 |
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