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ENE KB3700 Keyboard Controller Datasheet R0.1 2006

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发表于 2007-12-21 18:08:39 | 显示全部楼层 |阅读模式
Feature Summary$ w, y$ Z4 v6 A! S! U2 S. N3 ~
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Low Pin Count Host Interface (LPC)
# ~9 d& T. k7 v  SIRQ supporting IRQ1, IRQ12, SCI1 @* K4 R4 ^" {8 w+ P3 N
  I/O Address Decoding:
; r7 `/ f# \: V( N2 i4 m1 V5 k  KBC IO Port 60h/64h
% a" g5 I  t+ w& s  Programmable EC IO Port 62h/66h and 68h/6Ch) \1 y3 j  I, I+ T
  Programmable 4-byte Index I/O ports to access internal registers
6 C/ H1 h. r* R( ^5 I+ |) ^  One Programmable I/O write byte-address decoding
+ I. V! d/ f0 K, y8 v1 |. a- J
  i8 z$ a: `( ?/ \6 f2 x: |X-Bus Interface (XBI)
) K: v3 ?- P, B% {& U# U: b5 P  SPI Flash support, the operation frequency runs at least 50MHz.' k  z! l9 L. W7 [' v
  Addressable Memory range up to 24MB.5 l! s9 t. @" U) R, T1 @! B
  8051 64KB code memory can be mapped into 4 independent 16KB pages.7 h3 _3 R. A# E1 \$ @

# s& p5 ?$ y/ E& p) `: R( L  H8051 Microprocessor! a7 N* D# a; j& f4 s* l* B
  Industry 8051 Instruction set complaint with 3~5 cycles per instruction./ L, x6 e* x6 B* E) Z
  Programmable 8/16/32 MHz clock) U4 N4 |  r" w1 ^7 F
  Fast instruction fetching from XBI Interface
8 E1 y/ W# ]' v, c4 d; v  128 bytes and 2KB tightly-coupled SRAM
& R8 k4 X5 W! l$ X% d  24 extended interrupt sources.
4 q7 ~* x, [" m7 F+ g+ L9 e# N  Two 16-bit tightly-coupled timer6 {" M2 c1 Z$ S( Y. M1 H. F6 w

$ L2 h; n1 v+ A6 N8042 Keyboard Controller. A. K( E& l, w$ S
  8 Standard keyboard commands processed by hardware2 V3 h  a3 {8 I% y6 T
  Each hardware command can be optionally processed by firmware
6 e( H: q% Y. T7 d
1 ?7 X3 D$ ~7 x: D% n% O% S$ uEmbedded Controller (EC)7 ?7 p' O9 a$ d
  Five EC Standard Commands can be processed by hardware
/ o- z7 P: Q. P* A- q9 @% I  ACPI Specification 2.0 compliant7 c& q8 i9 z8 V2 X2 C, Y" v
  Support customer command by firmware
/ s  L1 d  q' h& I$ i  Programmable EC I/O port addressing (default 62h/66h)' i; Q! \+ Q& G8 R. K
3 z$ j; l6 g7 _& e* T8 W, u
Analog To Digital Converter (ADC)
# ]1 Y8 U, X6 N  U  6 built-in ADCs with 8-bit resolution.* m) A7 V) f3 N
  The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
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Pulse Width Modulator (PWM); v2 l, F+ ~: c* b3 @* F
  5 built-in PWMs4 G, p( j- }9 T# m3 {! H
  Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.% F8 o- w9 k2 {
  Configurable cycle time (up to 1 sec) and duty cycle.
& h& D& o. J; K1 w
9 m( {; z& V- u$ x6 `# QWatchdog Timer (WDT)0 E1 w! e* z' I/ z( }* w: L
  32.768KHz input clock with 20-bit time scale.1 w# D  H# Q% x9 ?
  8-bit watchdog timer interrupt and reset setting
# c( z: O# A3 c9 Y; z/ a" s# k" T8 ~* c" G3 S. g
General Purpose Timer (GPT)6 g- G6 m. B& K( B( o) F6 x8 F$ b7 B
  Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution3 Y* Q2 h8 }2 u4 @

' \4 x0 I1 u4 M4 z; U8 _General Purpose Wake-Up (GPWU)5 ?0 Z$ j0 W: e7 I3 L' P8 N! g" p
  All General Purpose Input pins can be configured to generate interrupts or wake-up event.
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General Purpose Input/Output (GPIO)# p+ B/ |, H9 W5 ~
  All I/O pins are bi-direction and configurable( S6 |* i$ k% E8 j
  All outputs can be optionally tri-stated$ @) w! U: S/ v( h! e- V, X
  All inputs equipped with pull-up, high/low active, edge/level trigger selection7 F. a) n& F1 S; {* c
  All GPIO pins are bi-direction, input and output.
/ J* l/ |4 s4 d9 L! ^5 f( O  Max. 43 GPIOs! l  m0 T6 C- q+ i, U0 W! r
. ^( K7 P# y1 [$ }
Power Management
; |: I7 R& S3 x  Sleep State: 8051 Program Counter (PC) stopped
3 Q( G$ `8 _* k% J  Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.& w! o; v* t* T9 e% W

4 y. h2 N1 Y% VTotal Pages: 40

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发表于 2008-12-4 12:05:57 | 显示全部楼层
many thanks! 有KB3310的DATASHEET吗?
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发表于 2008-12-4 16:10:26 | 显示全部楼层
Thanks a lot
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发表于 2009-4-9 15:27:40 | 显示全部楼层
这个SPEC还是太简单了,谁知道ENE在用SPI ROM时,prefetch的cache有多大?如果spi run over 50Mhz,我看到它的8051处理指令需要3~5个cycles,而且听说ENE用的免费的C code,那么你们在用的时候感觉perfermance怎么样?特别是处理PS2 device的时候。
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