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Feature Summary
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Low Pin Count Host Interface (LPC)
$ ^1 \. t4 c* |/ `% U SIRQ supporting IRQ1, IRQ12, SCI. _0 q4 U% g( \) @8 o% W
I/O Address Decoding:
- L+ U- a2 \8 E* E! L KBC IO Port 60h/64h/ _0 R3 E- R' L ^4 }0 N0 k5 l
Programmable EC IO Port 62h/66h and 68h/6Ch
2 B/ q7 d0 m+ I+ U+ q* _' J Programmable 4-byte Index I/O ports to access internal registers
0 K* U2 D2 t# O2 U; h% A; d7 B' _ One Programmable I/O write byte-address decoding
8 @' F, X8 J& a: ~8 C( b: K0 q! H7 r- C/ [3 V4 t: ~
X-Bus Interface (XBI). u6 `' T, t- ^ \+ @* T7 q7 N
SPI Flash support, the operation frequency runs at least 50MHz.
0 S9 F6 I3 Z, g Addressable Memory range up to 24MB.. ^2 W! V$ E* f# Q/ u! ^. C4 @7 n! S
8051 64KB code memory can be mapped into 4 independent 16KB pages.* a6 u4 E2 n4 l$ {! X0 Z* Y
5 c. q3 _7 ]# ?# S- N4 |! d8051 Microprocessor3 Q' W* @) r; O3 r/ g- i, |+ T
Industry 8051 Instruction set complaint with 3~5 cycles per instruction.* K, f3 w& b8 f$ f3 G, L! l* U& {+ X" d
Programmable 8/16/32 MHz clock& G! V$ d7 {* ^" v
Fast instruction fetching from XBI Interface0 G% y Q; [& A. X" x7 P
128 bytes and 2KB tightly-coupled SRAM
' d/ a3 g* Y% Q/ S7 ` 24 extended interrupt sources.( v% Y, h% b0 r g; r h
Two 16-bit tightly-coupled timer3 Z9 o, q( E. z7 u3 W
# U7 X. R) [' |! q6 L. A$ z/ h4 B8042 Keyboard Controller$ P- e7 }3 ?& L f7 P& q! B D
8 Standard keyboard commands processed by hardware
?% X( |* f( X0 r% Y* m+ J Each hardware command can be optionally processed by firmware
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Embedded Controller (EC)
" {) G1 c- o' N Five EC Standard Commands can be processed by hardware; j5 O7 d L% Z) g* k
ACPI Specification 2.0 compliant
! E, G! w- a: G Support customer command by firmware* ^0 j6 \1 l, C) @4 R- L/ ?
Programmable EC I/O port addressing (default 62h/66h)3 e2 }( x+ Y- l. S R; t# I; z
9 X5 [/ M8 P" \ s2 l
Analog To Digital Converter (ADC)" ^# p+ t \8 g
6 built-in ADCs with 8-bit resolution.
/ u" O- \8 k' x( u The ADC pins can be alternatively configured as General Purpose Inputs (GPI).. P! i+ }% y& ?4 _8 V/ |6 G+ z
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Pulse Width Modulator (PWM)
' W1 p& D. \- V; A1 Q 5 built-in PWMs6 T4 {( D" r" t9 e
Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.
) \/ `7 S+ Z Y7 j8 G Configurable cycle time (up to 1 sec) and duty cycle.
- I7 ?# [% B7 Q. v/ ~/ A5 N4 \+ Z
4 [& }$ T- b% @9 g# s- P! ]; F1 p5 ^Watchdog Timer (WDT)$ \0 ?0 l$ `+ a
32.768KHz input clock with 20-bit time scale." g G3 z5 X( C1 s
8-bit watchdog timer interrupt and reset setting
, a, n! F% M* u) P2 u
' Y4 o' Z9 p# }7 i6 e9 aGeneral Purpose Timer (GPT)
! e3 i2 n* q% p2 u! ] Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution5 H# ?1 o6 X/ v' j
1 w0 }7 O% M" J, Z+ EGeneral Purpose Wake-Up (GPWU)9 ]/ o& o2 m" u! e
All General Purpose Input pins can be configured to generate interrupts or wake-up event.8 b7 X1 ~ `5 C) x/ M$ s
% T' g8 Y5 M' h- q% hGeneral Purpose Input/Output (GPIO)
: @0 p I0 \* E7 E All I/O pins are bi-direction and configurable
. J' W4 H) H8 e" N# Y$ {0 s* u All outputs can be optionally tri-stated9 d7 C4 N" G& E- u/ B3 h
All inputs equipped with pull-up, high/low active, edge/level trigger selection
5 s2 l; Z- z+ k All GPIO pins are bi-direction, input and output.8 {$ v9 e4 \3 a6 I- Y: g2 E9 T
Max. 43 GPIOs. U( d: w- o' G6 ]
* S8 j7 k% s$ n5 qPower Management: ^4 J6 S& ?- y( @0 |( h# J
Sleep State: 8051 Program Counter (PC) stopped5 B3 e* T. Y! z8 ~4 ^
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.- ~7 N$ l6 s9 k' ]$ n8 L8 W
A1 Q% [& C$ H3 z* DTotal Pages: 40 |
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