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Programming Interface for Bus Master IDE Controller Revision 1.0
0 o3 V" D+ U9 R' \2 O( k' F1994/05/16, q# }$ Y: O* u9 I1 W5 I
+ |# v5 S- o& F* z" N YThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk
- l: U9 [( g/ G' V; h6 R, }& econtroller that directly moves data between IDE devices and main memory. By performing the IDE data9 A1 g9 O% Q# a' K
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
: p) L% C3 \9 M3 Tand improves system performance in multitasking environments.
9 C* K& [' P& s2 `9 N1 s; K+ f) Q$ Z4 N. q v* e& h/ ~$ H# \5 A; U
Until this specification is ratified, it is solely V9 N7 | U& N8 P
owned and maintained by:
2 j R! V) U1 @# cBrad Hosler, Intel Corporation- m4 S. m) M6 L
bwh@salem.intel.com (please comment using email)
) w0 }; _7 n0 p503-696-8431 |
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发表于 2010-7-14 14:53:56
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