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Programming Interface for Bus Master IDE Controller Revision 1.0: s$ }( ^: }0 p0 X( `
1994/05/16
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk r5 x/ _7 J4 J! v C
controller that directly moves data between IDE devices and main memory. By performing the IDE data( u% c1 A+ v+ r$ y) p3 @
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
k" }1 q/ Q7 f% ]and improves system performance in multitasking environments.* U" i! d6 y- o
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Until this specification is ratified, it is solely1 v- C$ ~' S/ \' }' I# [
owned and maintained by:: ~0 q( v6 t9 q* a- a) T+ X
Brad Hosler, Intel Corporation
% |7 `8 M r. O" j1 E% Lbwh@salem.intel.com (please comment using email)9 n B5 R# I9 h1 ^' t! x
503-696-8431 |
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