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Programming Interface for Bus Master IDE Controller Revision 1.0
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk) A5 S% Y4 h5 D ?0 ?0 l
controller that directly moves data between IDE devices and main memory. By performing the IDE data2 R- N2 K) \; C7 I
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
5 q) F n9 {/ ~" A$ aand improves system performance in multitasking environments.
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2 b9 J, ]: |/ N% G# WUntil this specification is ratified, it is solely
9 ? @/ [7 x) [( C. ]* r" n+ u7 Kowned and maintained by:
7 g2 L$ M+ V0 W! _% q4 R% ?* lBrad Hosler, Intel Corporation: ~5 `& S" c! W3 K8 w) b
bwh@salem.intel.com (please comment using email)
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发表于 2010-7-14 14:53:56
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