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PIC 、APIC(IOAPIC LAPIC) " S( ^: A6 `" u6 l/ b) ]! V
1. Overview4 S1 p+ A0 o6 a3 k: H7 `
1 Q: i+ N' v2 O1 N0 U7 vPIC全称Programmable Interrupt Controller,通常是指Intel 8259A双片级联构成的最多支持15个interrupts的中断控制系统。APIC全称Advanced Programmable Interrupt Controller,APIC是为了多核平台而设计的。它由两个部分组成IOAPIC和LAPIC,其中IOAPIC通常位于南桥中
! j& ^3 A9 `* f- _7 ]用于处理桥上的设备所产生的各种中断,LAPIC则是每个CPU都会有一个。IOAPIC通过APICBUS(现在都是通过FSB/QPI)将中断信息分派给每颗CPU的LAPIC,CPU上的LAPIC能够智能的决定是否接受系统总线上传递过来的中断信息,而且它还可以处理Local端中断的pending、nesting、masking,以及IOAPIC于Local CPU的交互处理。
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2. PIC
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" m0 V5 w+ ?6 [3 c8 D基于Intel 80x86的PC使用两片8259A级联的方式组成了可以管理15级中断向量的一个中断系统,下图是它的一个连接示意图。两片8259A,一片为Master,另一片为Slaver。其中Slaver的INT接到Master的IRQ2上。8259A有两种工作模式分别为编程和操作模式。BIOS初始化的时候会先通过IO port对8259A进行编程配置,在此之后8259A就可以响应来自外部设备的中断请求了。Master的IO address是0x20 0x21; Slaver的IO address是0xA0 0xA1。8 ?( n5 c/ ]8 a3 m
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为了能够正常的使用PIC来管理系统中断,就需要对它进行初始化。8259A支持两种类型的命令字,一类是初始化命令字ICW1~4,另一类是操作命令字OCW1~3,其中每一个命令字的各个bit都有其代表的特定意义。下述是一个初始化Master的一个sample code:
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MOV
4 X' m8 Y6 R% H% u0 L! PAL,00010001b
6 T- A# [0 t \ J6 W0 p6 Y$ _;级联,边沿触发,需要写ICW4' S& ~* q7 W$ k& i
OUT. C) s& x1 C$ A+ W- J( |$ L8 _
20H,AL
) o* U' ^ Q$ Y7 w ^;写ICW10 f0 t2 J' z9 {1 [/ ^" L( ]
MOV( y' h0 W% A, l: d
AL,01000000B ;中断类型号40H4 h! ^* `; X |, A4 G- y
OUT
3 t, k. T, s K21H,AL y% ]: }4 x! J6 W) Y% v% w
;写ICW2
# D/ g' C( B5 a- aMOV
( {2 @. U7 x+ B' SAL,00000100B;主片的IR2引脚从片
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21H,AL
" ?$ W' W: J5 p2 T6 `: J;写ICW3
+ o- y5 @. p- K, l ~7 UMOV
* j7 Z% _- H) q8 {AL,00010001B;特殊完全嵌套,非缓冲,自动结束
2 a7 _% M- D w' V6 q8 u& fOUT; N9 F( _$ N7 Y! ]& K6 q
21H,AL- _, S! R& x; F. \
;写ICW4
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) K6 p( Q/ }% G. Z. R0 f3. APIC2 y; g& E) ^5 ~. y ]
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Intel APIC由一组中断输入信号,一个24*64bit的Programmable Redirection Table(PRT),一组register和用于从APIC BUS(FSB/QPI)上传送APIC MSG的部件组成,当南桥的IO device通过IOAPIC的interrupt lines产生interrupt,IOAPIC将根据内部的PRT table格式化成中断请求信息,并将该信息发送给目标CPU的LAPIC,再由LAPIC通知CPU进行处理。下图是一个基于Intel APIC的连接示意图,如下图所示IOAPIC上有24个interrupt pin,
: o+ ^+ f( v8 |+ r/ [0 H每一个pin都对应一个RTE,所以针对每一个interrupt pin都可以单独设定它的mask,触发方式(level,edge trigger),中断管脚的极性,传送方式,传送状态,目的地,中断向量等。4 t3 N* _, n% H# U2 _
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Programmable Redirection Table详细格式如下所示:- h2 Z" ~+ N( Q" g
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Bit Description:
% |2 f0 K% X8 X; q2 R | [63:56] Destination Field—R/W.
% C4 r% T E( k! q3 q" cIf the Destination Mode of this entry is Physical Mode (bit 11=0), bits
! h$ M4 Z0 m6 ~. A; V$ K% e | [59:56] contain an APIC ID. If Logical Mode is selected (bit 11=1), the Destination Field& \5 B) r* X8 i& P* f
potentially defines a set of processors. Bits [63:56] of the Destination Field specify the logical
6 P$ H+ }) B. q, [8 Zdestination address.
; G5 Y3 x9 c4 _4 Q( f9 t0 q8 tDestination Mode IOREDTBLx[11] Logical Destination Address% v" x7 D6 I) D* v9 d
0, Physical Mode IOREDTBLx[59:56] = APIC ID+ @4 E- {3 }3 Q5 k- o6 q8 `. {
1, Logical Mode IOREDTBLx[63:56] = Set of processors
) P/ A; T+ \4 k! A; @* G* j | [55:17] Reserved.82093AA (IOAPIC) 8 S+ Z4 @- S; w* R$ T/ E( `$ V
| [16]0 f8 L5 h) w% H+ F3 t
Interrupt Mask—R/W.; J( A- `/ X* H1 e7 o+ Z# {, A: o
When this bit is 1, the interrupt signal is masked. Edge-sensitive
& ]! T: _# N j# k5 _interrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending).) y: O ?2 c6 }& ]7 q* i
Level-asserts or negates occurring on a masked level-sensitive pin are also ignored and have no3 A; _+ C: Y) F3 L
side effects. Changing the mask bit from unmasked to masked after the interrupt is accepted by/ K& v% B* H' l# x
a local APIC has no effect on that interrupt. This behavior is identical to the case where the
0 D' G6 M* R& {# c* \9 @" M/ R$ zdevice withdraws the interrupt before that interrupt is posted to the processor. It is software's2 H4 [& H! E" ~) T; k
responsibility to handle the case where the mask bit is set after the interrupt message has been
+ Z# Q k: f/ Daccepted by a local APIC unit but before the interrupt is dispensed to the processor. When this" F# ^, S9 P) e m$ z& D: r
bit is 0, the interrupt is not masked. An edge or level on an interrupt pin that is not masked
v% w8 P* g& Presults in the delivery of the interrupt to the destination.
# {! I# J9 H9 q | [15] Trigger Mode—R/W.
% u0 T% n4 b, U8 }8 O8 lThe trigger mode field indicates the type of signal on the interrupt pin that triggers an interrupt. 1=Level sensitive, 0=Edge sensitive.
4 u3 z" p/ _' D/ T | [14] Remote IRR—RO.
- F R7 n$ f N1 f& cThis bit is used for level triggered interrupts. Its meaning is undefined for edge triggered interrupts. For level triggered interrupts, this bit is set to 1 when local APIC(s) accept the level interrupt sent by the IOAPIC. The Remote IRR bit is set to 0 when an EOI message with a matching interrupt vector is received from a local APIC.9 J1 Z7 ]+ H) e3 D
| [13] Interrupt Input Pin Polarity (INTPOL)—R/W.7 `3 l' Q+ N+ R. J/ t% ]
This bit specifies the polarity of the interrupt
# o: ]" Y! _/ H8 d4 w& w8 P& Hsignal. 0=High active, 1=Low active.
9 O; ]. c6 h! o6 o/ ^2 e( Y | [12]
, D f! G( r, }7 ?' u3 g! h1 R; KDelivery Status (DELIVS)—RO.
4 l+ i; [, G, E! h# m3 Q( u9 _. `! hThe Delivery Status bit contains the current status of the/ l" x. s; F% I$ ~+ }
delivery of this interrupt. Delivery Status is read-only and writes to this bit (as part of a 32 bit
& u. t0 R- n# D) X$ u7 u( p$ Fword) do not effect this bit. 0=IDLE (there is currently no activity for this interrupt). 1=Send
$ n/ x ?. v2 ~/ ]2 b* ^Pending (the interrupt has been injected but its delivery is temporarily held up due to the APIC
3 H2 k$ H, C" s3 u5 t5 Ebus being busy or the inability of the receiving APIC unit to accept that interrupt at that time).5 G: r+ A: D" r8 m* J' \
| [11] Destination Mode (DESTMOD)—R/W.5 R8 g1 K; ]- R% }% w, o
This field determines the interpretation of the
3 L0 @3 R/ T3 [1 m6 o# c- |4 a) VDestination field. When DESTMOD=0 (physical mode), a destination APIC is identified by its ID.
5 H9 h' ~% @) d- `Bits 56 through 59 of the Destination field specify the 4 bit APIC ID. When DESTMOD=1 (logical mode), destinations are identified by matching on the logical destination under the control of theDestination Format Register and Logical Destination Register in each Local APIC.
- M* B' j6 ?' a/ ^% Q* q' {Destination Mode IOREDTBLx[11] Logical Destination Address 0, Physical Mode IOREDTBLx[59:56] = APIC ID1, Logical Mode IOREDTBLx[63:56] = Set of processorsE 82093AA (IOAPIC)
+ z8 L$ ]* K( Z, y | [10:8]Delivery Mode (DELMOD)—R/W." H5 u6 |% c1 J+ f$ H
The Delivery Mode is a 3 bit field that specifies how the APICs listed in the destination field should act upon reception of this signal. Note that certain% w! H% ^8 G. e) E1 L; p
Delivery Modes only operate as intended when used in conjunction with a specific trigger Mode.: ~ D5 M5 g9 K7 E3 Z5 |+ ], Z e4 E
These restrictions are indicated in the following table for each Delivery Mode.
, E! t+ {% X b' a' [' `4 }Mode Description
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Fixed Deliver the signal on the INTR signal of all processor cores listed in the
9 j) h" p c: h7 }- t' ]destination. Trigger Mode for "fixed" Delivery Mode can be edge or level.) b) @5 B( v2 L! k7 Q
001
& L* X2 p7 v5 u ULowest
2 Y" ^2 e4 `' a0 H8 C% }Priority Deliver the signal on the INTR signal of the processor core that is8 A. C$ _- h7 k
executing at the lowest priority among all the processors listed in the
& i! _8 J& Z# [/ ~/ s, V7 d+ Bspecified destination. Trigger Mode for "lowest priority". Delivery Mode. x. ]; b. F) T0 Y
can be edge or level.
1 t- _7 G! h _, R010
! p! `# g1 f4 C1 A1 j$ bSMI System Management Interrupt. A delivery mode equal to SMI requires an" N1 E5 z6 Y5 [( Y }3 `
edge trigger mode. The vector information is ignored but must be
F' S' M$ \6 x! t2 H& U- w7 W$ Sprogrammed to all zeroes for future compatibility.
: w( b+ q( X9 O& a$ N( n011
, E1 T5 [" l& j$ g3 z% {Reserved
' K3 u9 @& F) R8 b100
: k4 t2 @; Q0 ?/ [; e FNMI Deliver the signal on the NMI signal of all processor cores listed in the }9 L5 k8 j2 I
destination. Vector information is ignored. NMI is treated as an edge$ | w% K' W9 F( f6 ]. f9 k
triggered interrupt, even if it is programmed as a level triggered interrupt.4 p9 t4 _5 \7 Z# m+ [+ }
For proper operation, this redirection table entry must be programmed to
& ^2 m4 ~3 o B+ q: P1 S4 \' ]“edge” triggered interrupt.
: d- I/ O- W3 y- q$ F, m1 J: R101
& Z9 f5 C7 A5 P% u- L/ {3 TINIT Deliver the signal to all processor cores listed in the destination by( j6 u6 s! U1 E/ _4 h) w- u. `
asserting the INIT signal. All addressed local APICs will assume their
( e6 a: E# X0 L9 D% NINIT state. INIT is always treated as an edge triggered interrupt, even if! ^6 k/ Y9 b Z% m; b* m3 _7 E5 A# K
programmed otherwise. For proper operation, this redirection table entry/ P7 p, f+ T" G; ^0 h5 i+ o# k. q
must be programmed to “edge” triggered interrupt.- }" O2 a4 U: p
110( B% S4 ^# | S- f+ i6 F
Reserved: U/ p4 D# x; x( y5 g% R( h$ n
111
O& r( [. ?$ U5 nExtINT Deliver the signal to the INTR signal of all processor cores listed in the
" I; K$ `1 E. vdestination as an interrupt that originated in an externally connected
; A8 G/ x) g, l, P; j. u(8259A-compatible) interrupt controller. The INTA cycle that corresponds
+ h: q4 b/ G0 |" Q: uto this ExtINT delivery is routed to the external controller that is expected
# B+ ^3 K ^! f) C `to supply the vector. A Delivery Mode of "ExtINT"& l- }) F4 k/ N6 c9 N& |
requires an edge
1 S9 [% X( C6 q9 S4 t! o, h* \trigger mode.
: e* _ w( }6 U7 F. ~" v5 E8 v9 k3 x | [7:0] Interrupt Vector (INTVEC)—R/W:- q; X. T$ [0 m
The vector field is an 8 bit field containing the interrupt
2 [0 v2 X" Y" X: i& vvector for this interrupt. Vector values range from 10h to FEh.
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- x) h7 u1 l8 i3 ?0 w k. CREFF:! `. I1 j0 B! Y+ P
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《82093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)》' w5 k% Z7 ?" F3 {8 r& k
2.
6 H! R8 F# T) J《8259A PROGRAMMABLE INTERRUPT CONTROLLER(8259A/8259A-2)》. B5 N7 B( W+ H& k4 b1 E
3.
( B W8 ]6 {( d! B5 d _《Undocumented PC》
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; ^7 t0 ^% h& G' O8259A初始化编程
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* F' r5 V( E7 s7 t2 ~That’s all! ^# W w0 A8 {6 C% ?
* e9 X8 V/ S9 h2 q* SPeter& y5 z5 I4 N# |5 q- U* g: _
( ^: U! j' J" F6 K# p2010/10/07$ x+ T3 r N4 g! W; u8 K8 | g: s
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[ 本帖最后由 peterhu 于 2010-10-29 16:13 编辑 ] |
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